8085 Microprocessor
The salient features of 8085 μp are:
• It is a 8 bit microprocessor.
• It is manufactured with N-MOS technology.
• It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB) memory locations through A0-A15.
• The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 – AD7.
• Data bus is a group of 8 lines D0 – D7.
• It supports external interrupt request.
• A 16 bit program counter (PC)
• A 16 bit stack pointer (SP)
• Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
• It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock.
• It is enclosed with 40 pins DIP (Dual in line package).
1. 8085 PIN DIAGRAM
SIGNAL DIAGRAM
Properties
Single + 5V Supply
4 Vectored Interrupts (One is Non Maskable)
Serial In/Serial Out Port
Decimal, Binary, and Double Precision Arithmetic
Direct Addressing Capability to 64K bytes of memory
The Intel 8085A is a new generation, complete 8 bit parallel central processing unit (CPU). The 8085A uses a multiplexed data bus. The address is split between the 8bit address bus and the 8bit data bus. Figures are at the end of the document.
8085 Pin Description
The following describes the function of each pin:
A6 - A1s (Output 3 State)
Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0 address,3 stated during Hold and Halt modes.
AD0 - 7 (Input/Output 3state)
Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address) appear on the bus during the first clock cycle of a machine state. It then becomes the data bus during the second and third clock cycles. 3 stated during Hold and Halt
modes.
ALE (Output)
Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the address to get latched into the on chip latch of peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information. ALE can also be used to strobe the status information. ALE is never 3stated.
SO, S1 (Output)
Data Bus Status. Encoded status of the bus cycle:
S1 S0 PROCESS
0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH
S1 can be used as an advanced R/W status.
RD (Output 3state)
READ; indicates the selected memory or 1/0 device is to be read and that the Data Bus is available for the data transfer.
WR (Output 3state)
WRITE; indicates the data on the Data Bus is to be written into the selected memory or 1/0 location. Data is set up at the trailing edge of WR. 3stated during Hold and Halt modes.
READY (Input)
If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If Ready is low, the CPU will wait for Ready to go high before completing the read or write cycle.
HOLD (Input)
HOLD; indicates that another Master is requesting the use of the Address and Data Buses. The CPU, upon receiving the Hold request. will relinquish the use of buses as soon as the completion of the current machine cycle. Internal processing can continue. The processor can regain the buses only after the Hold is removed. When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.
HLDA (Output)
HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the buses one half clock cycle after HLDA goes low.
INTR (Input)
INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle of the instruction. If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted.
INTA (Output)
INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD during the Instruction cycle after an INTR is accepted. It can be used to activate the 8259 Interrupt chip or some other interrupt port.
RST 5.5
RST 6.5 - (Inputs)
RST 7.5
RESTART INTERRUPTS; These three inputs have the same timing as I NTR except they cause an internal RESTART to be automatically inserted.
RST 7.5 ~~ Highest Priority
RST 6.5
RST 5.5 o Lowest Priority
The priority of these interrupts is ordered as shown above. These interrupts have a higher priority than the INTR.
TRAP (Input)
Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt.
RESET IN (Input)
Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flipflops. None of the other flags or registers (except the instruction register) are affected The CPU is held in the reset condition as long as Reset is applied.
RESET OUT (Output)
Indicates CPlJ is being reset. Can be used as a system RESET. The signal is synchronized to the processor clock.
X1, X2 (Input)
Crystal or R/C network connections to set the internal clock generator X1 can also be an external clock input instead of a crystal. The input frequency is divided by 2 to give the internal operating frequency.
CLK (Output)
Clock Output for use as a system clock when a crystal or R/ C network is used as an input to the CPU. The period of CLK is twice the X1, X2 input period.
IO/M (Output)
IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and Halt modes.
SID (Input)
Serial input data line The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed.
SOD (output)
Serial output data line. The output SOD is set or reset as specified by the SIM instruction.
Vcc=+5 volt supply.
Vss=Ground Reference.
8085 Functional Description
The 8085A is a complete 8 bit parallel central processor. It requires a single +5 volt supply. Its basic clock speed is 3 MHz thus improving on the present 8080's performance with higher system speed. Also it is designed to fit into a minimum system of three IC's: The CPU, a RAM/ IO, and a ROM or PROM/IO chip.
The 8085A uses a multiplexed Data Bus. The address is split between the higher 8bit Address Bus and the lower 8bit Address/Data Bus. During the first cycle the address is sent out. The lower 8bits are latched into the peripherals by the Address Latch Enable (ALE). During the rest of the machine cycle the Data Bus is used for memory or l/O data.
The 8085A provides RD, WR, and lO/Memory signals for bus control. An Interrupt Acknowledge signal (INTA) is also provided. Hold, Ready, and all Interrupts are synchronized. The 8085A also provides serial input data (SID) and serial output data (SOD) lines for simple serial interface. In addition to these features, the 8085A has three maskable, restart interrupts and one non-maskable trap interrupt. The 8085A provides RD, WR and IO/M signals for Bus control.
Status Information
Status information is directly available from the 8085A. ALE serves as a status strobe.The status is partially encoded, and provides the user with advanced timing of the type of bus transfer being done. IO/M cycle status signal is provided directly also. Decoded So, S1 Carries the following status information:
HALT, WRITE, READ, FETCH S1 can be interpreted as R/W in all bus transfers. In the 8085A the 8 LSB of address are multiplexed with the data instead of status. The ALE line is used as a strobe to
enter the lower half of the address into the memory or peripheral address latch. This also frees extra pins for expanded interrupt capability.
Interrupt and Serial l/O
The8085A has5 interrupt inputs:
INTR,
RST5.5
RST6.5
RST 7.5
TRAP
INTR is identical in function to the 8080 INT. Each of the three RESTART inputs, 5.5, 6.5. 7.5, has a programmable mask. TRAP is also a RESTART interrupt except it is nonmaskable. The three RESTART interrupts cause the internal execution of RST (saving the program counter in the stack and branching to the RESTART address) if the interrupts are enabled and if the interrupt mask is not set. The non-maskable TRAP causes the internal execution of a RST independent of the state of the interrupt enable or masks.
The interrupts are arranged in a fixed priority that determines which interrupt is to berecognized if more than one is pending as follows: TRAP highest priority, RST 7.5, RST 6.5, RST 5.5, INTR lowest priority This priority scheme does not take into account the priority of a routine that was started by a higher priority interrupt. RST 5.5 can interrupt a RST 7.5 routine if the interrupts were re-enabled before the end of
the RST 7.5 routine. The TRAP interrupt is useful for catastrophic errors such as power failure or bus error. The TRAP input is recognized just as any other interrupt but has the highest priority. It is not affected by any flag or mask. The TRAP input is both edge and level sensitive.
Basic System Timing
The 8085A has a multiplexed Data Bus. ALE is used as a strobe to sample the lower 8bits of address on the Data Bus. Figure 2 shows an instruction fetch, memory read and l/ O write cycle (OUT). Note that during the l/O write and read cycle that the l/O port address is copied on both the upper and lower half of the address. As in the 8080, the READY line is used to extend the read and write pulse lengths so that the 8085A can be used with slow memory. Hold causes the CPU to relingkuish the bus when it is through with it by floating the Address and Data Buses.
System Interface
8085A family includes memory components, which are directly compatible to the 8085A CPU. For example, a system consisting of the three chips, 8085A, 8156, and 8355 will have the following features:
· 2K Bytes ROM
· 256 Bytes RAM
· 1 Timer/Counter
· 4 8bit l/O Ports
· 1 6bit l/O Port
· 4 Interrupt Levels
· Serial In/Serial Out Ports
In addition to standard l/O, the memory mapped I/O offers an efficient l/O addressing technique. With this technique, an area of memory address space is assigned for l/O address, thereby, using the memory address for I/O manipulation. The 8085A CPU can also interface with the standard memory that does not have the multiplexed address/data bus.
2. 8085 INTERNAL ARCHITECTURE
DESCRIPTIONS
3. 8085 Addressing Modes
The instructions MOV B, A or MVI A, 82H are to copy data from a source into a destination. In these instructions the source can be a register, an input port, or an 8-bit number (00H to FFH). Similarly, a destination can be a register or an output port. The sources and destination are operands. The various formats for specifying operands are called the ADDRESSING MODES. For 8085, they are:
i. Immediate addressing.
ii. Register addressing.
iii. Direct addressing.
iv. Indirect addressing.
i. Immediate addressing
Data is present in the instruction. Load the immediate data to the destination provided.
Example: MVI R,data
ii. Register addressing
Data is provided through the registers.
Example: MOV Rd, Rs
iii. Direct addressing
Used to accept data from outside devices to store in the accumulator or send the data stored in the accumulator to the outside device. Accept the data from the port 00H and store them into the accumulator or Send the data from the accumulator to the port 01H.
Example: IN 00H or OUT 01H
iv. Indirect Addressing
This means that the Effective Address is calculated by the processor. And the contents of the address (and the one following) is used to form a second address. The second address is where the data is stored. Note that this requires several memory accesses; two accesses to retrieve the 16-bit address and a further access (or accesses) to retrieve the data which is to be loaded into the register.
4. Instruction Set Classification
An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions, called the instruction set, determines what functions the microprocessor can perform. These instructions can be classified into the following five functional categories: data transfer (copy) operations, arithmetic operations, logical operations, branching operations, and machine-control operations.
Data Transfer (Copy) Operations
This group of instructions copy data from a location called a source to another location called a destination, without modifying the contents of the source. In technical manuals, the term data transfer is used for this copying function. However, the term transfer is misleading; it creates the impression that the contents of the
source are destroyed when, in fact, the contents are retained without any modification. The various types of data transfer (copy) are listed below together with examples of each type:
i. Between Registers.
Copy the contents of the register B into register D.
ii. Specific data byte to a register or a memory location.
Load register B with the data byte 32H.
iii. Between a memory location and a register.
From a memory location 2000H to register B.
iv. Between an I/O device and the accumulator.
From an input keyboard to the accumulator.
Arithmetic Operations
These instructions perform arithmetic operations such as addition, subtraction, increment, and decrement.
i. Addition - Any 8-bit number, or the contents of a register or the contents of a memory location can be added to the contents of the accumulator and the sum is stored in the accumulator. No two other 8-bit registers can be added directly (e.g., the contents of register B cannot be added directly to the contents of the register C). The instruction DAD is an exception; it adds 16-bit data directly in register pairs.
ii. Subtraction - Any 8-bit number, or the contents of a register, or the contents of a memory location can be subtracted from the contents of the accumulator and the results stored in the accumulator. The subtraction is performed in 2's compliment, and the results if negative, are expressed in 2's complement. No two other registers can be subtracted directly.
iii. Increment/Decrement - The 8-bit contents of a register or a memory location can be incremented or decrement by 1. Similarly, the 16-bit contents of a register pair (such as BC) can be incremented or decrement by 1. These increment and decrement operations differ from addition and subtraction in an important way; i.e., they can be performed in any one of the registers or in a memory location.
Logical Operations
These instructions perform various logical operations with the contents of the accumulator. AND, OR Exclusive-OR - Any 8-bit number, or the contents of a register, or of a memory location can be logically ANDed, Ored, or Exclusive-ORed with the contents of the accumulator. The results are stored in the accumulator.
i. Rotate- Each bit in the accumulator can be shifted either left or right to the next position.
ii. Compare- Any 8-bit number, or the contents of a register, or a memory location can be compared for equality, greater than, or less than, with the contents of the accumulator.
iii. Complement - The contents of the accumulator can be complemented. All 0s are replaced by 1s and all 1s are replaced by 0s.
Branching Operations
This group of instructions alters the sequence of program execution either conditionally or unconditionally.
i. Jump - Conditional jumps are an important aspect of the decision-making process in the programming. These instructions test for a certain conditions (e.g., Zero or Carry flag) and alter the program sequence when the condition is met. In addition, the instruction set includes an instruction called unconditional jump.
ii. Call, Return, and Restart - These instructions change the sequence of a program either by calling a subroutine or returning from a subroutine. The conditional Call and Return instructions also can test condition flags.
Machine Control Operations
These instructions control machine functions such as Halt, Interrupt, or do nothing. The microprocessor operations related to data manipulation can be summarized in four functions:
i. copying data
ii. performing arithmetic operations
iii. performing logical operations
iv. testing for a given condition and alerting the program sequence
Some important aspects of the instruction set are noted below:
1. In data transfer, the contents of the source are not destroyed; only the contents of the destination are changed. The data copy instructions do not affect the flags.
2. Arithmetic and Logical operations are performed with the contents of the accumulator, and the results are stored in the accumulator (with some expectations). The flags are affected according to the results.
3. Any register including the memory can be used for increment and decrement.
4. A program sequence can be changed either conditionally or by testing for a given data condition.
5. TIMING DIAGRAM
Q.) how to draw timing diagram?discuss the various steps
You first need to understand the machine cycles of 8085
The status signals are as follows
IO/M(bar) :--- 1 IO 0 Memory
S1 | S0 | Process
-----------------------------------------------------------
0 | 0 | Halt
0 | 1 | Write
1 | 0 | Read
1 | 1 | Opcode fetch
1)Opcode fetch ( Compulsory Machine cycle)
This cycle requires 4 T-states.
1st T state ALE is high and lower byte of address from PC(Program Counter) is placed on the multiplexed data/address bus.
In the second T-state, after checking the status of READY pin, RD(bar) goes low the opcode is placed on the data bus, This state continues in the 3rd T-State.
The fourth T-state is used by the uP to decode the instruction and to generate the relevant control signals. The state of the address bus is unspecified( This T-state is used by some DMA controllers to transfer data in hidden/transperant mode)
IO/M_ = 0 S1=1 S0=1
2)Memory read(for 1 byte)
Three T states, similar to the first 3 T states of opcode fetch( as first 3 states of opcode fetch is effectively memory read)
IO/M_ 0 S1 = 1 S0 = 0
3) Memory Write(for 1 byte)
Similar to Write but instead of RD bar WR bar is used. Also the data stays on the bus a little longer than READ*.
IO/M_ 0 S1 = 0 S0 = 1
4) & 5) IO write and read
Simlar to the above two, only IO/M_ = 1
These are the basic machine cycles you will require to draw timing diagrams for most instructions. There are additional cycles such as INTA bar and Bus idle. If anyone requires diagrams for these cycles, message me and i will explain them later.
Also some instructions like CALL require 6 T-state Opcode fetch. For this you can draw the 4 T state Opcode fetch but 4th T state extended to the fifth and sixth T state.
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How to find T States of 8085 Microprocessor.
How To Calculate Timing States In 8085 Microprocessor
CLK:-The clock is the machine clock it goes up and low.
A15-A8 :-These are the higher order address lines store only address,Here we put the higher order address.
AD7-AD0 :-These are the lower order address lines.This is a multi plexed Address/Data bus.Firstly we store lower order address in this and after that we put data in it.
ALE :- It is a positive going pulse which indicates that the bits on AD7-AD0 are address bits.This latches lower order bus and generate to seperate 8 address lines.
IO/M bar:-These are the status signals .Different signals give different results.
Opcode fetch (IO/M bar=0,S1=1,S0=1)
Memory Read (IO/M bar=0,S1=1,S0=0)
Memory Write (IO/M bar=0,S1=0,S0=1)
I/O Read (IO/M bar=1,S1=1,S0=0)
I/O Write (IO/M bar=1,S1=0,S0=1)
Interrupt Accow. (IO/M bar=1,S1=1,S0=1)
So this is the description of the timing diagram.Now we will know how to find the T states.
So for any instruction LDA,MVI,MOV ......etc.we have to fetch the operation code,for this the microprocessor goes to the memory location where it will find the machine code for that opcode.From this whatever has been there on the address goes through data bus to the instruction decoder which decodes the signal.
Lets take an example
MVI A,32H is the instruction.
So ,memory location 5000 in Hexa & machine code which is there for MVI is 00111110(assume only) ,ie 3E in Hexa.
For op code fetch the status signals are(IO/M=0,S1=1,S0=1),it places the memory address from program counter on the address bus and increment the program counter to 5001.Thus,50 H goes to higher order bus and 00H goes to lower order bus.The Ale signal goes high during T1 which latches
the lower order bus.At T2 the 8085 asserts RD bar signal,which enables the memory,and the memory places the byte 3E on the data bus.Then 8085 places opcode in the instruction register and disables RD bar signal.The fetch cycle is completed in T3 state.During T4 state 8085 decodes the opcode.
and finds out second byte to read.After the T3 state,the contents of the bus A15-A8 are unspecified and AD7-AD0 goes high impedance.
For opcode fetch 4T states required.
After the opcode fetch 8085 goes again to the memory and places the next address 5001 on the address bus and increments the program counter.The second signal identifies as memory read thus,the status signals are (IO/M=0,S1=1, S0=0),the same thing happen as
it has been for opcode accept the decode.So for reading 3T states are required.
AS general rule :-
If there is 1 byte instruction we will require minimum 4T states.
If there is 2 byte instruction we will require minimum 7T states.
If there is 3 byte instruction we will require minimum 10T states.
For opcode fetch 4T states.
read 3T state.
write 3T state.
Thus in above example which is 2 byte instruction we will require 4T states for opcode fetch and then 3T states for reading the data.Thus total 7T states.
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